Step-by-Step Guide to a 2×2 Bit Multiplier in Verilog

Analyzing Gate-Level Delay in a 2×2 Bit Multiplier

Overview

Analyzing gate-level delay examines how long the output bits of a 2×2 multiplier take to stabilize given propagation delays of individual logic gates. A 2×2 multiplier multiplies two 2-bit inputs (A1A0 × B1B0) to produce a 4-bit product P3P2P1P0. Typical implementation uses AND gates to form partial products, then adders (half/full adders) to sum them.

Typical Gate-Level Structure

• Partial products (PP):
  • PP0 = A0·B0 → contributes directly to P0
  • PP1 = A1·B0
  • PP2 = A0·B1
  • PP3 = A1·B1
• Sum network:
  • P0 = PP0
  • Use a half adder (HA) to sum PP1 and PP2 → sum S1 and carry C1
    • P1 = S1
  • Use a half/full adder arrangement to add PP3 and C1 → produce P2 and carry to P3
    • P2 = sum of PP3 and C1
    • P3 = final carry

Hardware mapping:

• AND gates for PPs
• One HA for PP1+PP2 (XOR + AND)
• One HA or full adder stage for PP3 + C1 (XOR/AND plus final carry OR)

Delay Components (assume gate delays)

• t_AND = propagation delay of an AND gate
• t_XOR = delay of an XOR gate
• t_OR = delay of an OR gate (used in carry generation if HA implemented via OR)
• For a half-adder: t_HA_sum = t_XOR (inputs are PP1, PP2), t_HA_carry = t_AND
• For final carry/sum stage depends on using HA or full adder; commonly:
  • t_FA_sum ≈ t_XOR + t_XOR (two XORs in series or XOR-tree)
  • t_FA_carry ≈ t_AND + t_OR (or gate combination for carry)

Critical Path Analysis

Identify the longest path from any input bit to any product bit.

• P0 path: A0,B0 → AND → P0

  • Delay = t_AND

• P1 path: A0/A1 and B0/B1 to PP1/PP2 → XOR for HA sum → P1

  • Delays: max(t_AND for PP1, t_AND for PP2) + t_XOR
  • Delay = t_AND + t_XOR

• P2 path (critical candidate): several possibilities; common longest:

  • A1,B1 → PP3 (t_AND)
  • PP1/PP2 produce C1 via HA carry (t_AND) — but C1 available after t_AND
  • Then PP3 and C1 summed in adder:
    • If implemented as HA: sum uses XOR with PP3 and C1 (t_XOR) but C1 arrival may be t_AND from earlier stage
    • Total delay ≈ max(t_AND (PP3), t_AND (C1 path)) + t_XOR
    • Considering C1 depends on A0,A1,B0,B1, total often = t_AND (to generate PP1/PP2) + t_XOR (HA sum) for P1, then carry path t_AND to produce C1, then t_XOR to sum with PP3. Practically:
  • Conservative critical-path delay = t_AND (PP1/PP2) + t_AND (carry generation) + t_XOR (final sum) — but optimized implementations differ.

• P3 path: final carry out from adding PP3 and C1

  • Carries typically use AND/OR chain: delay ≈ t_AND (for partial carry) + t_OR
  • Total may be t_AND (for PP1/PP2 carry) + t_AND (for PP3 & C1) + t_OR

Example using typical delays (illustrative):

• t_AND = 1 unit, t_XOR = 2 units, t_OR = 1 unit
  • P0 = 1
  • P1 = 1 + 2 = 3
  • P2 ≈ 1 (PP3) vs C1 path (1 for PP1/PP2 AND + 1 for HA carry) then XOR 2 → ~4
  • P3 ≈ C chain 1 + 1 + 1 = 3–4 depending on implementation

How to Compute Precisely

1. Draw gate-level netlist with actual gate implementations for HAs/FAs.
2. Assign vendor/process-specific delays (t_pd) for each gate type.
3. Perform static timing analysis:
   • Compute arrival times forward from inputs.
   • For each gate: t_arrival_out = max(t_arrival_ins) + t_pd_gate.
4. Identify the maximum arrival time at product outputs — that’s the critical-path delay.

Optimization Strategies

• Replace ripple-style adder stages with faster adders (carry-lookahead) — overkill for 2×2 but instructive.
• Use XOR implementations with lower delay or construct using complex gates.
• Implement carry generation with AOI/OAI cells to reduce logic depth.
• Pipeline (not typical for 2-bit) or restructure to balance path lengths.

Practical Notes

• For small multipliers, gate fanout and wiring delay may dominate in advanced technologies.
• Use static timing tools from your target foundry/FPGA to get accurate numbers.